1. Technical Field
The present invention relates to the field of logic simulation and, more particularly, to reducing the size of a netlist during simulation.
2. Description of the Related Art
A logic simulator is a software tool, which is capable of performing functional and timing simulations for digital electronic designs which are written in a hardware description language (HDL) such as VHSIC Hardware Description Language (VHDL) or Verilog. The VHSIC acronym stands for Very High Speed Integrated Circuits. VHDL and Verilog are HDLs used to design and document electronic systems. Verilog, for example, permits hardware designers to define signals at a very high level of abstraction. The abstracted signal representations can be translated to actual pins on a microchip using any of a variety of commercial electronic design automation (EDA) software tools. Verilog and VHDL are both object-oriented languages and thus have the equivalent of classes or design units and instances or objects. An object or an instance is an instantiation of a class. In Verilog, classes are called “modules” and an instance can be an instantiation of the module. Both Verilog and VHDL are typed languages, meaning that declaration statements are used to make known the types of the objects. A module is declared and then instantiated to yield a module instance. It should be noted that a second module declaration cannot be nested within a first module declaration in Verilog, but instances of a second module can be nested within a first module.
Verilog (and VHDL) have the language feature that when the functional description contained in the module in Verilog (and in the architecture of the entity/architecture pair in VHDL), i.e., y=f(x), where x is the input port and y the output port, is missing (or deleted), the signals are “fed-through” unchanged. For example, in the case where module IA is connected to module IE and module IB is connected to module IC (where “I” indicates an instance of a module), then if IB is an instance of a module without any functional mapping, i.e., empty, then IB serves as a connection point between IA and IC, like a signal wire.
As the size of field programmable gate arrays (FPGAs) and other devices become inordinately larger, the size of netlists describing such devices have correspondingly grown. In turn, the time and cost of simulating and verifying such devices using such large netlists have also increased. With respect to simulation of FPGAs, several techniques have been used in an attempt to overcome problems encountered with simulation using such large netlists. Small array sizes are used where possible. Alternatively, increased memory on the servers can be utilized and finally faster servers can be used. Smaller array sizes are effective for bringing a new family of parts up to speed with verification, but ineffective when larger members of the family are desired to be verified. Increased memory has helped for a time, but array sizes (and therefore the transistor count) kept increasing on components that required overall verification or simulation. Faster servers only help to an extent, but memory and the lack thereof still present inadequacies in simulation and verification solutions for today's significantly larger architectures.
In consequence, the amount of time required to simulate and verify large field programmable gate arrays and other devices represented by netlists using current software simulation tools can be significant as the sheer number of calculations necessary can be quite extensive. What is needed is an improved technique for reducing the time and resources required for simulation, verification and other processing of hardware described using hardware description language which in turn translates into utilization of fewer processing resources, less simulation time, and therefore reduced time required for design and implementation of such hardware.